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CA3420S/3 Supplier, CA3420S/3 on Stock |
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| CA3420S/3 CA3420S/3 PDF The X25128 is a CMOS 131,072-bit serial EEPROM, internally organized as 16K x 8. The X25128 features a Serial Peripheral Interface (SPI) and software proto- col, allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. CA3420S/3 Datasheet • Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life • Logic Level Gate Drive Can Be Driven by Logic ICs • Miniature SOC8 Surface Mount Package Saves Board Space • Diode Is Characterized for Use In Bridge Circuits • Diode Exhibits High Speed, With Soft Recovery • IDSS Specified at Elevated Temperature • Avalanche Energy Specified • Mounting Information for SOC8 Package Provided MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1) CA3420S/3 Suppliers The CA3420S/3 is a voice recorder IC which contains A/D and D/A converters to digitize and reproduce voice signals. An anti-alias/smoothing filter, AGC circuit, MIC preamplifier, and speaker power amplifier are used to smooth the input voice and set the output voice to a certain volume while minimizing the number of extra components needed. The recording time depends on the size of the external memory. n Custom Reset Threshold voltages: For other voltages between 2.2V and 5.0V in 10mV increments, contact National Semiconductor Corp. n No external components required n Manual-Reset input n RESET (CA3420S/3) or RESET (CA3420S/3) outputs n Precision supply voltage monitor n Factory programmable Reset and Watchdog Timeout Delays n Available in micro SMD package for minimum footprint n 0.5% Reset threshold accuracy at room temperature n 2% Reset threshold accuracy over temperature extremes n Reset assertion down to 1V VCC (RESET option only) n 28 µA VCC supply current For a MOSFET with a uniformly doped substrate, the threshold voltage is proportional to the square root of the applied source-to-body voltage. The SD5000 family has a non-uniform substrate, and the VGS(th) behaves somewhat differently. Figure 7 shows the typical VGS(th) variation as a function of the source-to-body voltage VSB. During soft-start, and all the time during normal converter operation, this pin represents the output of the error amplifier. Use this pin, in combination with the FB pin, to compensate the voltage-control feedback loop of the converter. I2C interface select / I2C RESET (active low, asynchronous). If ISEL is high, then the I2C interface is active. Default values for the I2C registers can be found in the I2C register descriptions section. If ISEL is low, then I2C is disabled and the chip configuration is specified by the configuration pins (BSEL, DSEL, EDGE, VREF) and state pin (PD). If ISEL is brought low and then back high, the I2C state machine is reset. The register values are changed to their default values and are not preserved from before the reset. Monitor sense / programmable output 1. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin has an open-drain output and is only 3.3-V tolerant. An external 5-kΩ pullup resistor connected to VDD is required on this pin. When I2C is disabled (ISEL = low), a high level indicates a powered-on receiver is detected at the differential outputs. A low level indicates a powered-on receiver is not detected. This function is valid only in dc-coupled systems. When I2C is enabled (ISEL = high), this output is programmable through the I2C interface (see the I2C register descriptions). |
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