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CA3420S Supplier, CA3420S on Stock |
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| CA3420S CA3420S PDF The LIBERATOR™ CL10KA family offers you all of the time-to- market benefits of designing with programmable logic. Simply use Altera FLEX 10KA FPGAs to prototype and verify the design. Then, take five minutes to submit the bitstream using Clear Logic's web site! Within eight weeks, your system can be in volume production using compatible Clear Logic devices. CA3420S Datasheet 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CA3420S Suppliers The voice-band audio processor (VBAP) is designed to perform the transmit encoding analog/digital (A/D) conversion and receive decoding digital/analog (D/A) conversion, together with transmit and receive filtering, for voice-band communications systems. The device operates in either the 15-bit linear or 8-bit companded (µ-law or A-Law) mode, which is selectable through the I2C interface. From a 2.048-MHz master clock input, the VBAP generates its own internal clocks. Input /output clock. I/O CLOCK receives the serial input and performs the following four functions: 1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK with the multiplexer address available after the fourth rising edge. 2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input begins charging the capacitor array and continues to do so until the last falling edge of I/O CLOCK. 3. The remaining 11 bits of the previous conversion data are shifted out on DATA OUT. Data changes on the falling edge of I/O CLOCK. 4. Control of the conversion is transferred to the internal state controller on the falling edge of the last I/O CLOCK. The CA3420S is a true one-port, surface-acoustic-wave (SAW) resonator in a surface-mount, ceramic case. It provides reliable, fundamental-mode, quartz frequency stabilization of local oscillators operating at 317.5 MHz. This SAW is designed for 318 MHz superhet receivers with 500 kHz IF (Philips UAA3201T). Applications inlude remote-control and wireless security receivers operating in the USA under FCC Part 15, in Canada under DoC RSS-210, and in Australia. SYMBOL PARAMETER Gate Driver IGONGATE Pin Current IGOFFGATE Pin Current IGPDGATE Pin Short-Circuit Pull-Down ∆VGATEExternal Gate Voltage (VGATEn C VEE) Output Voltage Sense VPGPower Good Threshold Voltage IVOUTOut Pin Bias Current NOTES: 1. See Test Conditions under TEST CIRCUITS AND WAVEFORMS. 2. This parameter is guaranteed but not production tested. 3. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.2ns at CL = 50pF. Since this time constant is much smaller than the rise and fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 4. Minimums are guaranteed but not production tested. 5. Maximum toggle frequency for Sx control input (pass voltage > VCC, VIN = 5V, RLOAD > 1MΩ, no CLOAD). |
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