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CA3420AE Supplier, CA3420AE on Stock |
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| CA3420AE CA3420AE PDF Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller (without reset- ting the serial sequence). To pause, HOLD must be CA3420AE Datasheet 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions over 1 second may affect reliability. CA3420AE Suppliers The CA3420AE is a true one-port, surface-acoustic-wave (SAW) resonator in a surface-mount ceramic case. It provides reliable, fundamental-mode, quartz frequency stabilization of local oscillators operating at approximately 304.3 MHz. This SAW is designed for 315 MHz superhet receivers with 10.7 MHz IF. Applica- tions include automotive keyless-entry receivers operating in the USA under FCC Part 15, in Canada under DOC RSS-210, and in Italy. Active high TTL compatible signal used to turn on an external current source to provide current to charge the battery. Active high TTL compatible signal available to turn on a discharge circuit. Polling detect indicator. An active low turns on an external indicator to show the controller is polling for the presence of the battery. Maintenance mode indicator. An active low turns on an external indicator showing the battery is either in the topping charge, maintenance charge or auxiliary condition mode. This signal is also applied with the out-of-temperature range indicator when the controller is in a cold battery charge mode. The indicator flashes during the auxiliary discharge mode. Charge mode indicator. An active low turns on an external indicator to show the controller is either in a soft start charge or fast charge. Out-of-temperature range indicator. An active low turns on an external indicator showing the battery is out of the normal fast charge temperature range. Tri-level input used with the SEL1 pin to program the device for the desired charge rate. Ground. Ground. Tri-level input used with the SEL0 pin to program the device for the desired charge rate. Master reset signal. A logic low pulse greater than 700 ms initiates a device reset. An external resistor and capacitor sets the frequency of the internal clock. Selects temperature slope and/or voltage slope termination. Tri-level input used with the AUX1 pin to program the device for an auxiliary operating mode. Tri-level input used with the AUX0 pin to program the device for an auxiliary operating mode. Thermistor or thermal switch input for temperature sensing. Open circuit (no battery) voltage reference. An external resistor divider on this pin sets the open circuit voltage reference used to detect the presence of a battery. Battery voltage normalized to one cell with an external resistor divider. Ground. Device supply =+5.0 VDC Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. See Applications Section for information on temperature de-rating of this device." Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. The HC374, HCT374, HC574, and HCT574 are octal D-type flip-flops with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the LOW to HIGH transition of clock (CP). The output enable (OE) controls the 3-state outputs and is independent of the register operation. When OE is HIGH, the outputs are in the high-impedance state. The 374 and 574 are identical in function and differ only in their pinout arrangements. The MC100EP016A is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the ECLinPS™ family MC100E016 with higher operating speed. The counter features internal feedback to TC gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all−one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated. COUT and COUT provide differential outputs from a single, non−cascaded counter or divider application. COUT and COUT should not be used in cascade configuration. Only TC should be used for a counter or divider cascade chain output. A differential clock input has also been added to improve performance. The 100 Series contains temperature compensation. |
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