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CA339M Supplier, CA339M on Stock |
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| CA339M CA339M PDF FUNCTIONAL DESCRIPTION The STLC3065 is a device specifically developed for WLL application. It is based on a SLIC core, on purpose optimised for this application, with the addition of a DC/DC converter controller and a dual port in order to ful- fil the WLL requirements. The SLIC core performs the standard feeding, signalling and transmission functions. It can be set in three different operating modes via the D0, D1, D2 pins of the control logic inter- face (0 to 3.3V logic levels). The loop status is carried out on the DET pin (active low).The DET pin is an open drain output to allow easy interfac- ing with both 3.3V and 5V logic levels. The three possible SLIC core operating modes are: Power Down (PWD) CA339M Datasheet Pulse duration 100 µs and duty cycle 2%. Technique should limit TJ C TC to 10C maximum. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85C. CA339M Suppliers The CA339M is a high frequency, dual MOSFET driver specifically designed to drive two power N-Channel MOSFETs in a synchronous rectified buck converter. These drivers combined with a FAN53168 Multi-Phase Buck PWM controller and power MOSFETs form a complete core voltage regulator solution for advanced microprocessors. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. The CA339M contains an 8254 compatible timer/counter. This device contains three 16-bit counters, each with its own clock input, gate input and output pin. The clock input to counter 0 is driven from an on board frequency source which is selected by LK1 to be 1MHZ, 100KHZ or 10KHZ, and the output can be used to generate an interrupt signal. The clock and gate inputs for the remaining counters are derived from I/O lines 24-27, and the output signals are routed to I/O lines 16-17 via LK3-4. The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals. 20 VB Output VoltageVBCB6.87.58.2V 21 VB Output CurrentIBCB25--mA 22 FG,DMVOLFG,DM-1.0-V Output Voltage 23 FG,DMROLFG,DM-200400Ω Output Resistance 24 LVSD Output Voltage LVSDON Vcc,MU,10.0 11.5 12.9V 25 LVSD recover Voltage LVSDOFF MV,MW10.1 12.0 13.0V 26 LVSD reset hysterisis Vrh0.10.50.9V Note 1. Pull Up Resistance and Pull Down Resistance are typically 200 kΩ. Note 2. Please see Note 2 in item 6 for determining the frequency of SAW wave. Note 3. The amplitude of SAW(VSAWW) is determined by the following equation, VSAWW=VSAWH-VSAWL (V) Note 4. The equivalent circuit around FG and DM terminal is shown in Fig. 2 Note 5. LVSD: Low Voltage Shut Down |
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