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CA339E Supplier, CA339E on Stock |
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| CA339E CA339E PDF The W29EE012 includes a data polling feature to indicate the end of a programming cycle. When the W29EE012 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is completed. DQ7 will show the true data. CA339E Datasheet Meets or Exceeds ANSI Standard EIA/ TIA-422-B Operates From a Single 5-V Power Supply Drives Loads as Low as 50 Ω up to 15 Mbps TTL- and CMOS-Input Compatibility Output Short-Circuit Protection Interchangeable With National Semiconductor™ DS9638 CA339E Suppliers The CA339E is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, highCperformance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words of 18 bits, fabricated with Motorolas highCperformance siliconCgate BiCMOS technology. The device integrates input registers, a 2Cbit counter, high speed SRAM, and high drive registered output drivers onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Syn- chronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 C A15), data inputs (D0 C D17), and all control signals except output enable (G) are clock (K) controlled through positiveCedgeCtriggered non- inverting registers. This device contains output registers for pipeline operations. At the rising edge of K, the RAM provides the output data from the previous cycle. Output enable (G) is asynchronous for maximum system design flexibility. Burst can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the CA339E (burst sequence imitates that of the i486 and Pentium) and controlled by the burst address advance (ADV) input pin. The following pages provide more detailed information on burst controls. Write cycles are internally selfCtimed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex offCchip write pulse generation and provides increased flexibility for incoming signals. Dual write enables (LW and UW) are provided to allow individually writeable bytes. LW controls DQ0 C DQ8 (the lower bits), while UW controls DQ9 C DQ17 (the upper bits). This device is ideally suited for systems that require wide data bus widths and cache memory. See Figure 2 for applications information. Both devices offer a high speed disable feature allowing the output to be configured into a high impedance state. This al- lows multiple outputs to be connected together for cascading stages while the OFF channels do not load the output bus. They operate on voltage supplies of 5 V and are offered in 8- and 14-lead plastic DIP and SOIC packages. Up to 97% Efficiency 2MHz PWM Switching 800mA Guaranteed Output Current Low 48µA Quiescent Current Power-Saving Modes: Pulse-Group, Pulse-Skip, Forced-PWM Mode 0.75V to 2.5V Preset Output Range (in 50mV Increments) Voltage-Positioning Load Transients 5mVP-P Output Ripple Tiny 2.2µH Inductor 10µF Ceramic Output Capacitor Low 0.1µA Shutdown Current No External Schottky Diode Required Soft-Start with Zero Inrush Current 170ms (min) RESET Output Small 12-Pin, 4mm x 4mm Thin QFN Package The CA339E represents Sensorys next generation speech and analog I/O mixed signal processor. The CA339E is designed to bring advanced speech I/O features to cost sensitive embedded and consumer products. Based on an 8-bit microcontroller, the CA339E- 4128 integrates speech-optimized digital and analog processing blocks into a single chip solution capable of accurate speech recognition; high quality, low data-rate compressed speech; and advanced music. Products can use one or all features in a single application. The AMS2911 series develops a 1.25V reference voltage between the output and the adjust terminal. Placing a resistor between these two terminals causes a constant current to flow through R1 and down through R2 to set the overall output voltage. This current is normally the specified minimum load current of 10mA. Because IADJ is very small and constant it represents a small error and it can usually be ignored. |
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