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CA339BF Supplier, CA339BF on Stock |
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| CA339BF CA339BF PDF This pin is internally biased at the reference voltage level, VR; VR = +VS/2 Ð 650 mV. The DC voltage level at this pin forms an internal reference for the voltage levels at pin 3, 8, 11 and 12. Pin 10 must be bypassed to ground with a 0.1 mF capacitor. CA339BF Datasheet a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. CA339BF Suppliers IC=10uA IC=100mA IE=10uA VCB=60V VCB=60V, VEB(off)=3V VEB=3V IC=150mA, IB=15mA IC=500mA, IB=50mA IC=150mA, IB=15mA IC=500mA, IB=50mA VCE=10V, IC=100uA VCE=10V, IC=1mA VCE=10V, IC=10mA VCE=10V, IC=150mA VCE=10V, IC=500mA VCE=1V, IC=150mA IC=20mA VCE=20V, f=100MHz Low VCC Write Lock Out During power-up and power-down , are locked out for VCC less than VLKO If VCC<VLKO, the command inputs is dis- abled and the device is reset to the read mode. On power-up, if CE\=VIL, WE\= VIL, and OE\=VIH, the device does not accept commands on the raising edge of WE. The device automati- cally powers up in the read mode. Low VCC Write Lock Out During power-up and power-down , are locked out for VCC less than VLKO If VCC<VLKO, the command inputs is dis- abled and the device is reset to the read mode. On power-up, if CE\=VIL, WE\= VIL, and OE\=VIH, the device does not accept commands on the raising edge of WE. The device automati- cally powers up in the read mode. Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. Alternatively, a relatively short tREC with a long t DO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in Figure 7 with a description of the events in Figure 9. Figure 2 on page 4 shows one sample configuration of a SPORT using the precision clock generators to interface with an I2S ADC and an I2S DAC with a much lower jitter clock than the serial port would generate itself. Many other SRU configura- tions are possible. |
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