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CA3388 Supplier, CA3388 on Stock |
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| CA3388 CA3388 PDF IN1-IN4 (Pins 1, 2, 3, 4): Sequenced Power Supply Monitor. Connect this pin to an external resistive divider between each sequenced power supply and GND. During Power On sequencing, 0.61V (typ) at this pin indicates that the sequenced power supply (enabled with each of the OUT1-OUT4 pins) has reached the desired Power On sequence voltage. A hysteresis current (programmed by the HYS pin) is sourced out of each of the IN1-IN4 pins after the 0.61V threshold is detected. During the Power Off sequence, 0.61V at this pin indicates that the sequenced power supply has reached the desired Power Off voltage. The hysteresis current is removed after the 0.61V thresh- old is detected. CA3388 Datasheet • Low output noise = 4.0nA/rt-Hz • High-performance laser diode driver • Pin compatible with EL6257 • Voltage-controlled output current source to 150 mA per channel, requiring one external set resistor per channel • Current-controlled output current source to 150 mA per channel • Rise time = 1.0 ns • Fall time = 1.1 ns • On chip oscillator with frequency and amplitude control by use of external resistors to ground • Oscillator to 500 MHz • Oscillator to 100 mA pk/pk • Single +5V supply (10%) • Disable feature for power-up protection and power savings • TTL/CMOS control signals CA3388 Suppliers The device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. NOTES 1To order MIL-STD-883, Class B processed parts, add/883B to part number. Contact your local sales office for military data sheet. For U.S. Standard Military Drawing (SMD) see DESC drawing #5962-87700. 2E = Leadless Ceramic Chip Carrier: N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. COMMAND SEQUENCES: The device powers on in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. After the completion of a program or an erase cycle, the device enters the read mode. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. Prior to the low-going pulse on the CE or WE signal, the address input may be latched by a low-to-high transition on the AVD signal or the rising edge of the first clock pulse when AVD is low, whichever occurs first. If the AVD is not pulsed low, the address will be latched on the falling edge of the WE or CE pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by enter- ing the command sequences. The CA3388 Voice over IP (VoIP) and Voice over ATM (VoATM) Communication Board is a high-density, hot-swappable, compactPCI resource board with a capacity of up to 192 ports, supporting all necessary functions for voice and fax streaming over IP or ATM networks. The board is powered by AudioCodes Voice over Packet Processors, and supports up to 192 independent and concurrent channels with the most demanding algorithms, such as G.168 compliant echo cancellation and G.723.1 and G.729A voice compression. A 128 channel configuration is available to enable cost-effective entry level solutions. Notes: 4. Power supply sequencing is required. Power must be applied such that, VDD (3.3V) supply must not trail CVDD (3.3V/5V) supply on power-up by more than 1V until VDD reaches its normal operating voltage. Ramps can be simultaneous as long as the above condition is maintained. 5. For detailed information about data retention after 100K cycles, please see Cypress qualification report. |
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