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CA3310D Supplier, CA3310D on Stock |
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| CA3310D CA3310D PDF The ADC1241 is a CMOS 12-bit plus sign successive ap- proximation analog-to-digital converter On request the ADC1241 goes through a self-calibration cycle that adjusts positive linearity and full-scale errors to less than g LSB each and zero error to less than g1 LSB The ADC1241 also has the ability to go through an Auto-Zero cycle that corrects the zero error during every conversion The analog input to the ADC1241 is tracked and held by the internal circuitry and therefore does not require an external sample-and-hold A unipolar analog input voltage range (0V to a 5V) or a bipolar range ( b5V to a 5V) can be accom- modated with g5V supplies The 13-bit word on the outputs of the ADC1241 gives a 2s complement representation of negative numbers The digi- tal inputs and outputs are compatible with TTL or CMOS logic levels CA3310D Datasheet N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. Using trench technology the device features very low on-state resistance and has integral zener diodes giving ESD protection. It is intended for use in DC-DC converters and general purpose switching applications. CA3310D Suppliers Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds300C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability Thermal protection is achieved by monitoring the temperature of the motor windings with PTC sensors. These sensors can be the Klixon BA series or any other compatible PTC sensor rated Mark A or B. If the windings exceed the rated trip temperature the sensor undergoes a rapid change in resistance relative to the change in temperature. As a result of this change, the CA3310D0/CA3310D1/CA3310D modules' internal relays de-energize the control coil of the external line break contactor. The oscillator configuration allows design of either RC or crystal oscillator circuits. A high level on the CLEAR accomplishes the reset function, i.e. all counter outputs are made low and the oscillator is disabled. A negative transition on the clock input increments the counter. Ten kinds of divided output are pro- vided ; 4 to 10 and 12 to 14 stage inclusive. The maximum division available at Q12 is 1/16384 f os- cillator. Switching between active and standby conditions via the Chip Enable pin may produce tran- sient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. When RESET is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs are allowed. In addition, when RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. |
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