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CA3310AM Supplier, CA3310AM on Stock |
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| CA3310AM CA3310AM PDF The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipelined delays associated with the part. CA3310AM Datasheet Operating at C40˚C is not damaging but allowance must be made by the user for increased gate trigger current, latching current and holding current as well as slow turn-on (see application note AN4840 Gate Triggering and Gate Characteristics). Working in the range between room temperature and 125˚C gives the best compromise between ease of operation and operational life. CA3310AM Suppliers 2. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. Hynix CA3310AM-H/L series incorporates SPD(serial presence detect). Serial presence detect function is imple- mented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. The digital inputs are CMOS-compatible and equipped with a built-in pull-up resistor with a typical rating of 85 kW to VCC. The input threshold totals VTH = 0.57 ´ VCC with a typical hysteresis of 100 mV. The inputs are designed for an input voltage of -0.2 V to VCC + 0.6 V. DEVICE OPERATION The device supports the I2C protocol. This is sum- marized in Figure 2. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24M01 device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driv- en High. A Stop condition terminates communica- tion between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EE- PROM Write cycle. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a success- ful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. Current Loop Voltage Compliance Settling Time (to 0.1% of FS)2 Output Impedance (Current Mode) Accuracy 3 Monotonicity Integral Nonlinearity Offset (0 mA or 4 mA) (TA = +25C) Offset Drift Total Output Error (20 mA or 24 mA) (TA = +25C) Total Output Error Drift PSRR4 |
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