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CA3310AE Supplier, CA3310AE on Stock |
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| CA3310AE CA3310AE PDF Line sensitive electronics cause an instantaneous transfer to battery power if utility power is lost, or a brownout condition is detected. When line voltage is present and stabilized, the transfer circuitry switches back to normal operation and begins recharging the battery. The transfer circuitry can be tested via a momentary test switch located on the housing. CA3310AE Datasheet The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. Power consumption is greatly reduced when the device is placed in the standby mode. CA3310AE Suppliers Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvola- tile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Notes: 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD , normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 5. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is started. 6. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal Write time of the memory is defined by the overlap of CE1 LOW / CE2 HIGH, and WE LOW. CE1 and WE must be LOW along with CE2 HIGH to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. The Micrel CA3310AE is a simple and accurate lithium ion battery charger. Featuring a built-in pass transistor, precision programmable current limiting (5%), and precision voltage termination (1.5% over temperature) all in a very small package, the CA3310AE packs full functionality into a small space. The Micrel CA3310AE is a simple and accurate lithium ion battery charger. Featuring a built-in pass transistor, precision programmable current limiting (5%), and precision voltage termination (1.5% over temperature) all in a very small package, the CA3310AE packs full functionality into a small space. DISTINCTIVE CHARACTERISTICS n Ideal for Fiber-In-The-Loop (FITL) applications n Low standby power n C21 V to C58 V battery operation n On-chip battery switching and feed selection n On-hook transmission n Two-wire impedance set by single external |
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