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CA330954 Supplier, CA330954 on Stock |
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| CA330954 CA330954 PDF Current Loop Voltage Compliance Settling Time (to 0.1% of FS)2 Output Impedance (Current Mode) Accuracy 3 Monotonicity Integral Nonlinearity Offset (0 mA or 4 mA) (TA = +25C) Offset Drift Total Output Error (20 mA or 24 mA) (TA = +25C) Total Output Error Drift PSRR4 CA330954 Datasheet • High Performance CPU Interface − Supports Slot-1 and Socket 370 (Intel Pentium IITM and CeleronTM) processors − 66 / 100 MHz CPU Front Side Bus (FSB) − Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions − Five outstanding transactions (four In-Order Queue (IOQ) plus one input latch) − Supports WC (Write Combining) cycles − Dynamic deferred transaction support − Sleep mode support − System management interrupt, memory remap and STPCLK mechanism CA330954 Suppliers System Level Fault Protection Features • Auto-restart and cycle by cycle current limiting functions handle both primary and secondary faults • On-chip latching thermal shutdown protects the entire system against overload Enhanced DMA support Automatic DMA (ADMA) mode for fully CPU-inde- pendent transfer of large bulk or ISO packets DMA controller, together with the ADMA logic, can transfer a large block of data in 64-byte packets via the USB Automatic Data PID toggling/checking and NAK packet recovery (maximum 256x64 bytes of data = 16K bytes) The FM1246 consists of a TV tuner, an FM radio tuner and an IF section, all on a single PCB. The front-end is assembled in a metal housing made of a rectangular tin-plated steel frame, with front and rear covers, which have soldered contacts to the frame. The two phono or IEC antenna connectors (female for TV, male for FM radio) are mounted on one side of the frame for the TV/FM signal inputs. All other connections are made via pins at the bottom. The SY89825U is a High Performance Bus Clock Driver with 22 differential LVPECL output pairs. This part is designed for use in low voltage (2.5V, 3.3V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either LVDS or LVPECL by the CLK_SEL pin. The LVDS input includes a 100Ω internal termination, thus eliminating the need for external termination. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control. The SY89825U features low pin-to-pin skew (35ps max.) performance previously unachievable in a standard product having such a high number of outputs. The SY89825U is available in a single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew. Input load capacitors are placed on the CY22050 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply, and temperature changes. |
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